1. Field of the Invention
The present invention relates to a three-dimensional multi-gate device and a fabricating method thereof, and more particularly, to a three-dimensional multi-gate device having a stress-adjusting layer and a fabricating method thereof.
2. Description of the Prior Art
With increasing miniaturization of semiconductor devices, various three-dimensional multi-gate devices have been developed. The three-dimensional multi-gate device is advantageous for the following reasons. First, the manufacturing processes of three-dimensional multi-gate devices can be integrated into the traditional logic device processes, and thus are more compatible. Furthermore, due to the structural particularity of the three-dimensional multi-gate device, traditional shallow trench isolation is not required. In addition, since the three-dimensional structure increases the overlapping area between the gate and the substrate, the channel region is more effectively controlled. This therefore reduces drain-induced barrier lowering (DIBL) effect and short channel effect. Moreover, the channel region is longer under the same gate length. Therefore, the current between the source and the drain is increased.
Although the three-dimensional multi-gate device is advantageous for many reasons, the carrier mobility still requires to be improved.